The field of the present invention is that of circuit modeling, and more specifically that of modeling of circuit designs using phase synchronous equations.
Logic design of, for example, integrated circuits typically includes a design phase and a verification phase for determining whether a design works as expected. Verification uses software simulation to avoid the cost of first implementing a design in hardware to verify it.
Designs to be verified can be represented in a hardware description language (HDL) xe2x80x9cmodelxe2x80x9d that, through simulation, can predict the behavior of a proposed design independently of its physical implementation. The model may be expressed at varying levels of abstraction: some levels may be highly abstract, representing a circuit only in terms of its behavior, while other levels may include more details of physical implementation. One commonly utilized abstraction level is referred to as xe2x80x9cregister transfer level,xe2x80x9d or RTL.
Writing models in HDL presents challenges. Accurate modeling of designs may call for a significant level of implementation detail, but too much implementation detail can introduce functional bugs. Generally, the number of bugs in a model is proportional to its size (i.e., the amount of code required to specify the model ). More abstract models tend to be smaller in size and may therefore contain fewer bugs. Abstract models also allow for faster simulation and better exploration of design space.
One known technique which has been applied in modeling logic designs and which provides for a useful degree of abstraction and conciseness, is the use of synchronous equations. For example, a combinational AND gate with two inputs, xe2x80x9caxe2x80x9d and xe2x80x9cbxe2x80x9d, and output xe2x80x9ccxe2x80x9d, may be modeled as c(i)=a(i) b(i) (where the AND operation is indicated by concatenation), where index i serves as a clock counter, and a(i) corresponds to a stable value of signal a at clock count i. As another example, a flip-flop with input x and output y may be modeled as y(i)=x(ixe2x88x921). Such synchronous equations have been used to model, for example, iterative synchronous algorithms used in DSP (digital signal processing) systems, in control theory and CAD (computer-aided design) for control systems, and in systolic computations as well as other types of computations.
One drawback of using synchronous equations to model logic designs, however, is that they are ill suited to model high-speed circuits. High-speed circuits such as, for example, high-performance microprocessors, require circuit designs that produce very accurate clock phases, utilize transparent latches, and support multiple clock methodologies. Standard synchronous equations cannot model the behavior of circuits with transparent components, multi-phase clocking, and multiple clocks.
An additional problem that arises in the coding of models of logic designs is that typically clock phase information must be manually coded for each signal in a design, which is a tedious, error-prone and time-consuming process. This manual process must be repeated if the clock phase information changes as a result of design changes.
A method and system are needed to address the foregoing concerns.